CVSS3
Attack Vector
LOCAL
Attack Complexity
HIGH
Privileges Required
HIGH
User Interaction
REQUIRED
Scope
CHANGED
Confidentiality Impact
HIGH
Integrity Impact
HIGH
Availability Impact
HIGH
CVSS:3.1/AV:L/AC:H/PR:H/UI:R/S:C/C:H/I:H/A:H
CVSS4
Attack Vector
LOCAL
Attack Complexity
HIGH
Privileges Required
HIGH
User Interaction
PASSIVE
CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:P/VC:H/SC:H/VI:H/SI:H/VA:H/SA:H
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel® Processor may allow a privileged user to potentially enable escalation of privilege via local access.
OS | Version | Architecture | Package | Version | Filename |
---|---|---|---|---|---|
Debian | 12 | all | intel-microcode | < 3.20240813.1~deb12u1 | intel-microcode_3.20240813.1~deb12u1_all.deb |
Debian | 11 | all | intel-microcode | < 3.20240813.1~deb11u1 | intel-microcode_3.20240813.1~deb11u1_all.deb |
Debian | 999 | all | intel-microcode | < 3.20240813.1 | intel-microcode_3.20240813.1_all.deb |
Debian | 13 | all | intel-microcode | < 3.20240813.1 | intel-microcode_3.20240813.1_all.deb |
CVSS3
Attack Vector
LOCAL
Attack Complexity
HIGH
Privileges Required
HIGH
User Interaction
REQUIRED
Scope
CHANGED
Confidentiality Impact
HIGH
Integrity Impact
HIGH
Availability Impact
HIGH
CVSS:3.1/AV:L/AC:H/PR:H/UI:R/S:C/C:H/I:H/A:H
CVSS4
Attack Vector
LOCAL
Attack Complexity
HIGH
Privileges Required
HIGH
User Interaction
PASSIVE
CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:P/VC:H/SC:H/VI:H/SI:H/VA:H/SA:H