CVE-2023-34326

2024-01-0517:15:08

[email protected]

web.nvd.nist.gov

amd-vi

caching

invalidation

guidelines

malfunction

dma

mappings

memory

nvd

cve-2023-34326

7.8 High

CVSS3

Attack Vector

LOCAL

Attack Complexity

LOW

Privileges Required

LOW

User Interaction

NONE

Scope

UNCHANGED

Confidentiality Impact

HIGH

Integrity Impact

HIGH

Availability Impact

HIGH

CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H

7.5 High

AI Score

Confidence

High

0.0004 Low

EPSS

Percentile

9.2%

JSON

The caching invalidation guidelines from the AMD-Vi specification (48882—Rev
3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction
(see stale DMA mappings) if some fields of the DTE are updated but the IOMMU
TLB is not flushed.

Such stale DMA mappings can point to memory ranges not owned by the guest, thus
allowing access to unindented memory regions.

Affected configurations

NVD

Node

xenxen

CPENameOperatorVersion
xen:xenxeneq*

CPE	Name	Operator	Version
xen:xen	xen	eq	*

CNA Affected

[
  {
    "defaultStatus": "unknown",
    "product": "Xen",
    "vendor": "Xen",
    "versions": [
      {
        "status": "unknown",
        "version": "consult Xen advisory XSA-442"
      }
    ]
  }
]