x86/AMD: missing IOMMU TLB flushing

ISSUE DESCRIPTION

The caching invalidation guidelines from the AMD-Vi specification (48882—Rev 3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction (see stale DMA mappings) if some fields of the DTE are updated but the IOMMU TLB is not flushed.
Such stale DMA mappings can point to memory ranges not owned by the guest, thus allowing access to unindented memory regions.

IMPACT

Privilege escalation, Denial of Service (DoS) affecting the entire host, and information leaks.

VULNERABLE SYSTEMS

All Xen versions supporting PCI passthrough are affected.
Only x86 AMD systems with IOMMU hardware are vulnerable.
Only x86 guests which have physical devices passed through to them can leverage the vulnerability.