CVE-2023-34326 x86/AMD: missing IOMMU TLB flushing

2024-01-0516:30:57

XEN

www.cve.org

amd-vi

caching invalidation

hardware malfunction

stale dma mappings

memory access

7.9 High

AI Score

Confidence

High

0.0004 Low

EPSS

Percentile

9.2%

JSON

The caching invalidation guidelines from the AMD-Vi specification (48882—Rev
3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction
(see stale DMA mappings) if some fields of the DTE are updated but the IOMMU
TLB is not flushed.

Such stale DMA mappings can point to memory ranges not owned by the guest, thus
allowing access to unindented memory regions.

CNA Affected

[
  {
    "defaultStatus": "unknown",
    "product": "Xen",
    "vendor": "Xen",
    "versions": [
      {
        "status": "unknown",
        "version": "consult Xen advisory XSA-442"
      }
    ]
  }
]